module mult_div(x,y,clk,out,overflow,op);
	input [15:0]x,y;			// 输入浮点数
	output reg[15:0]out;			// 输出浮点数
	output reg overflow;			// 溢出标志位
	input clk;					// 时钟信号
	input op;
	reg	[5:0]xE,yE,zE;			// 5位阶码+1位,移码表示
	reg [11:0]xF,yF,zF;			// 1位数符+10位尾数+1位前置1
	reg [2:0] state;			// 状态变量
	wire flag;					// 决定是否输出
	parameter START = 3'b000,ZEROCHECK= 3'b001,ADD_E = 3'b010,MULT = 3'b011,STANDER=3'b100,OVER=3'b101,DIV = 3'b110;
	
	assign flag = (state == OVER) ? 1 : 0;
	always@(posedge clk)
	begin
		if(flag == 1)
			out <= {zF[11],zE[4:0],zF[9:0]};
		case(state)
		START:
		begin
			xE <= {1'b0,x[14:10]};		// 阶码提取
			yE <= {1'b0,y[14:10]};
			xF <= {x[15],1'b1,x[9:0]};	// 从左到右分别是数符,隐藏位,尾数
			yF <= {y[15],1'b1,y[9:0]};
			state <= ZEROCHECK;
		end
		ZEROCHECK:									// 检查x,y是否有一个是0
		begin
			if(x == 0)
			begin
				{zE,zF} <= 0;
				state <= OVER;
			end
			else if(y == 0)
			begin
				{zE,zF} <= 0;
				state <= OVER;
			end
			else
				state <= ADD_E;
		end
		ADD_E:										// 阶码相加部分
		begin
		if(op == 0)
			begin
				zE <= xE + yE - 4'b1111;					// 二者相加后减去偏阶
				state <= MULT;
			end
		else if(op == 1)
			begin
				zE <= xE + 4'b1111 - yE;				//	xE作为被除数，先加上一个值再减去yE
				state <= DIV;
			end
		end
		MULT:										// 相乘部分								
		begin
			zF[10:0] <= xF[10:0] * yF[10:0];
			if((xF[11] ^ yF[11]) == 0)
				zF[11] <= 0;
			else
				zF[11] <= 1;
			state <= STANDER;
		end
		DIV:
		begin
			zF[10:0] <= xF[10:0] / yF[10:0];
			if((xF[11] ^ yF[11]) == 0)
				zF[11] <= 0;
			else
				zF[11] <= 1;
			state <= STANDER;
		end
		STANDER:
		begin
			if(zE[5] == 1'b1)
				overflow <= 1;
			else
				overflow <= 0;
			state <= OVER;
		end
		OVER:
		begin
			state <= START;
		end
		default:
		begin
			state <= START;
		end
		endcase
	end




endmodule